Sr. Analog IC Design Engineer - IVR Architecture Team
# Sr. Analog IC Design Engineer - IVR Architecture Team **Ferric, Inc.** · United States · `Remote` · `Full Time` 💼 **Уровень роли:** `Senior` 💰 **Компенсация:** `$135,000 – $170,000` 🕒 **Статус:** *Опубликовано: сегодня* · *Источник: Himalayas (JSON API)* --- ### Top Skills & Match 🎯 **Ключевой стек роли:** `[Analog-Design-Engineer]` `[IVR-Architecture-Engineer]` `[Power-Electronics-Engineer]` `[Integrated-Circuit-Design]` `[Ic-Design-Engineer]` --- ### About the Role About Ferric, Inc. Ferric is a technology startup based in New York City that is pioneering an entirely new approach to power delivery for Integrated Circuits and Electronic Assemblies. This approach leverages Ferric’s integration of thin-film magnetic inductors with CMOS technology to enable a significant improvement in the integration density and efficiency of voltage regulators (VRs) compared with current commercially available technologies. As a Ferric Analog IC Design Engineer on the IVR Architecture Team, you contribute to building the most advanced cutting edge integrated voltage regulators, leveraging Ferric’s industry-leading on-chip inductor technology. These products have applications ranging from KW-scale AI processors to ultra-low power Mobile platforms including wearable devices. Your primary responsibilities include ownership of system architectures, defining specifications for system sub-blocks, and ensuring that the system design meets product target requirements. Primary Responsibilities: - Drive system architecture design to optimize product performance targets such as efficiency, density, load current transient response, input supply rejection, and reference tracking performance for Ferric IVRs. - Identify specifications for sub-blocks within the overall system given system level requirements. - Maintain and implement various types of system-level models to pioneer novel power conversion and control solutions. - Perform system-level simulations and verification with a focus on performance prediction through bench correlation. - Design, simulation, and layout of analog IPs pertinent to IVRs as needed. - Champion system level performance goals across design, applications, and testing teams to ensure optimal results. Minimum Qualifications: - MSEE with analog design experience. - Strong knowledge of control theory and stability analysis. - Strong knowledge of switching power converter design. - Deep knowledge of CMOS analog circuit design, knowledge of digital circuit design. - Experience with custom IC design flows and tools. Preferred Qualifications: - BSEE + 8 years, MSEE + 5 years, or PhD + 2 years experience in power or RF IC design, or related field. Candidates demonstrating exceptional competency outside these ranges may be considered. - Experience designing high switching frequency integrated voltage regulators. - Experience designing ICs in standard CMOS. Exotic semiconductors are a plus. - Deep understanding of process and device physics concepts. - Familiarity with mixed signal verification methodologies. - Experience with Monte Carlo analysis. - Familiarity with analog design EDA tools such as Cadence Virtuoso, schematic capture, LVS, DRC, SPICE simulation, parasitic extraction, electromagnetics simulators. - Experience with bench-level validation, characterization, and debug of full ICs and IC sub-systems. - Languages: Verilog, Verilog-AMS, Python, Perl, Tcl, Cadence Skill, MATLAB, etc. Desired Characteristics & Attributes: - Passionate, self-starter with strong commitment to relentless execution - Excellent written and verbal communication skills required - Ability and desire to proactively steer and coordinate design activities across a multidisciplinary design team. Location: - New York, NY Logistics: - Remote or in NYC office - Annual salary range for this position $135,000-170,000 Originally posted on Himalayas
- Analog-Design-Engineer
- IVR-Architecture-Engineer
- Power-Electronics-Engineer
- Integrated-Circuit-Design
- Ic-Design-Engineer
Наблюдалась 2026-10-03, впервые 2026-10-03, источник — Himalayas (JSON API).