Silicon Physical Design Engineer V

Fresh Consulting is a design-led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate. We bring together amazing UX designers, sophisticated developers, digital strategists, and top-notch engineers to help companies create fresh experiences that connect humans, systems, and machines. We've been growing fast and need someone to help us continue to manage the delivery of high-quality work in a fast-paced environment.

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Title: Silicon Physical Design Engineer V Duration: 1-year contract with likely extension (up to 2 years) Location: Remote – must work Pacific Time (PST) hours Benefits: Employee benefits at 100% including Medical, PTO, Holiday Pay, 401K Plan and much more!

Role:

• Set up and maintain PPRTL and PTPX power analysis flows (average and time-based/peak power)
• Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations; handle long-waveform and windowed analysis
• Correlate RTL-level power estimates against gate-level signoff power and explain deltas
• Produce per-block, per-hierarchy, and per-workload power breakdowns; identify top power contributors and clock/datapath waste
• Recommend and evaluate power reduction opportunities (clock gating efficiency, datapath gating, memory power, idle leakage)
• Automate flows and reporting with TCL, Python, and Make-based build systems; integrate into regression/CI
• Document methodology and support design teams in interpreting results
• Perform PPA optimization with Fusion Compiler
• Perform RTL and netlist-level power analysis
• Perform post-processing and scripting on report log files for format conversion, data analysis, and information extraction
• Set up, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)
• Implement select blocks at RTL and UPF
• Document and communicate findings clearly

Qualifications:

• 10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer
• Experience with power estimation tools and synthesis, plus some physical design
• Knowledge of power trade-offs in design and back-end implementation
• Hands-on experience in scripting and data analysis

Preferred Qualifications:

• Hands-on production experience with Synopsys (PPRTL, PTPX/PrimePower, VCS, Verdi, DC, ICC, FC) and/or Cadence (Joules), PowerArtist
• Ability to debug simulation-to-power flow issues end to end
• Strong scripting skills: TCL, Python, and Excel-based scripting and data post-processing tools, model fitting, data visualization and analysis; comfortable with Linux and large compute/job-scheduling environments
• Experience in low power design, tools, and methodologies, including UPF power intent specifications
• Silicon power characterization, including some power modeling/profiling experience at the IP/SoC level
• Interest or experience in machine learning hardware for AR/VR products

Education: BS in Electrical Engineering, Computer Science, or equivalent experience

Compensation offered will be determined by factors such as location, level, job-related knowledge, skills, and experience. Range is $75hr to $115hr USD per hour.

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Originally posted on Himalayas