Senior Verification — LSU (Load/Store Unit) and Data Cache
# Senior Verification — LSU (Load/Store Unit) and Data Cache **Semidynamics** · 08029 Barcelona, Barcelona provincia · `On-site` 🕒 **Статус:** *Опубликовано: 26 дней назад* · *Источник: Indeed* --- ### About the Role ID: SV-LSU Description Role summary Own verification of the Load/Store Unit, data cache and bus interfaces for a CPU/GPU core — the block handling memory ordering, address generation, cache/TLB interaction, forwarding, and exception handling. Contribute to drive the LSU from RTL freeze to tapeout-quality sign-off. Responsibilities Define and own the LSU verification plan: functional coverage, testplan, checkers, and closure criteria Build/extend UVM testbench components for LSU (drivers, monitors, scoreboards, memory models) Develop directed and constrained-random tests covering store-to-load forwarding, memory ordering (RISC-V WMO model), speculative loads, vector accesses, misaligned/split accesses, exceptions/faults, and pipeline hazards Drive formal verification for ordering/coherence properties where simulation coverage is weak Debug RTL/testbench failures in collaboration with design; triage and root-cause Track and close functional/code coverage; report verification status to program s Mentor verification engineers; review testbench code and testplans Interface with architecture, design, and DV s on other units to resolve cross-unit issues. Why Seynamics? Work at one of Europe's most promising deep-tech semiconductor scale-ups. Accelerated development path. 4 days per week in the Barcelona office (city center), 1 WFH day. 1 week of work from everywhere in the world. Competitive package. A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking. Requirements Required qualifications BS/MS in EE/CE/CS, 5+ years in ASIC functional verification. Strong SystemVerilog/UVM experience; hands-on testbench architecture Deep understanding of memory subsystems: cache hierarchies, TLBs, memory consistency models, load/store pipelines Knowledge of RISC-V ISA and privileged specification is mandatory Knowledge of AMBA AXI4, AXI5Lite and CHI is mandatory Experience with coverage-driven verification and regression management Debugging complex RTL failures using waveform tools (Verdi/DVE or similar) Preferred Formal verification experience (JasperGold or similar) applied to memory ordering/coherence Knowledge of CPU architecture and memory execution pipeline Prior LSU, cache, or memory-controller verification specifically Experience with RISC-V, ARM, or x86 memory models Scripting (Python/Perl) for verification infrastructure and regression automation Prior team or mentorship experience Nice to Have Emulation platforms (Veloce, ZeBu) Familiarity with fuzzing techniques (AFL++) Knowledge of SystemC/C++ testbenches Essential Soft Skills An adversarial, gap-seeking mindset — instinctively asks "who actually checks this?" — collaborative relationship with the whole core. Clear communication across DV, design, and software teams; writes verification plans others can follow. SENIOR
Наблюдалась 2026-09-15, впервые 2026-08-21, источник — Indeed.