Principal Engineer, Analog Mixed-Signal Desig
# Principal Engineer, Analog Mixed-Signal Desig **SiTime** · Germany · `Remote` · `Full Time` 💼 **Уровень роли:** `Senior` 🕒 **Статус:** *Опубликовано: сегодня* · *Источник: Himalayas (JSON API)* --- ### Top Skills & Match 🎯 **Ключевой стек роли:** `[Analog-Mixed-Signal-Design]` `[CMOS-Circuit-Design]` `[Integrated-Circuit-Design]` `[Semiconductor-Engineering]` `[Hardware-Engineering]` `[Mixed-Signal-Design-Engineer]` `[Analog-Design-Engineer]` `[Principal-ASIC-Design-Engineer]` `[Principal-Design-Engineer]` `[Principal-Electrical-Engineer]` `[Principal-Engineer]` --- ### About the Role About SiTime SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com . Job Summary The Principal CMOS Analog Mixed-Signal Design Engineer will be responsible for lead and supervise circuit design and chip development projects. Define device and circuit architectures for next-generation products. Design circuit blocks for future products. Review circuits and architectures to ensure high quality designs. Propose improvements and implement methodologies for IC development Responsibilities: - Develop precision timing circuit architectures, design innovative circuits with aggressive technical performance specifications, performing transistor-level design and simulations - Plan and execute circuit designs that address demanding frequency stability, phase noise and power consumption, silicon die area specifications - Perform technology, architecture, circuit design, and parametric design trade-offs to accomplish spec-compliant designs - Ensure first-pass success on Analog CMOS circuit solutions, fully leveraging SiTime ’s innovative MEMS technology offerings - Collaborate with Digital Design Engineers, CAD, Systems Engineering, ATE Engineering and Applications teams to design chips with DFT, DFM, achieve rapid silicon bring-up and fast time-to-production release - Deploy robust design methodology and ensure comprehensive design reviews - Supervise and guide Senior Analog Circuit Designers - Supervise Analog Circuit Physical Design Layout and edit layouts - Perform post-layout parasitic-extraction and back-annotated simulations to validate design across Process, Voltage, Temperature - Perform requisite Monte Carlo Analysis on key circuits to ensure Six-Sigma quality and yields - Participate in bring-up of silicon prototypes - Initiate Design-of Experiments for Root Cause Analysis, investigate anomalous observations in silicon across PVT conditions, and propose solutions - Drive other projects as needed by management or as business needs change Qualifications & Requirements: - MS Degree in Electrical Engineering, PhD preferred - Minimum 10 years of high-performance analog circuit design experience - Proven track record at each stage of the following: 1. Circuit Architecture development and technical feasibility studies 2. Design partitioning for phase noise / power budgeting 3. Writing detailed block-level specifications 4. Detailed design, test bench development, and simulation of basic analog building blocks and one or more of the following: - ADCs, DACs, Temperature Sensors, PLL, high-speed Operational Amplifiers, On-chip Regulators, Band gap Circuits - Expert-level experiential knowledge of architecting and implementing ultra low-jitter, power-efficient Frac-N PLLs - Experiential knowledge of ultra-low phase-noise design, power supply noise considerations, device matching, parasitic extraction, signal integrity, ESD - Supervision of Junior and Senior Analog Design Engineers - Supervision of layout and editing of critical blocks - Chip-level design and verification of complex mixed-signal chips - Chip validation, Characterization, Qualification, adherence to production release to production - 3 years of prior lead/supervisory/managerial experience preferred Desired Characteristics & Attributes: - Passionate, self-starter with strong commitment to flawless execution - Curious, with the desire to solve any problem that comes your way - Excellent written and verbal communication skills required - Ability to work well with others in a fast-paced collaborative team environment Compensation Range: At SiTime , we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals – reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success. Learn More about SiTime : Review theGet to Know SiTime section of our career page to explore our culture, values, and what makes us unique. - Innovation on Top – Philosophies of Innovation with Rajesh Vashist - Fabrication Knowledge – An Interview with Rajesh Vashist - SiTime Corporation – YouTube Originally posted on Himalayas
- Analog-Mixed-Signal-Design
- CMOS-Circuit-Design
- Integrated-Circuit-Design
- Semiconductor-Engineering
- Hardware-Engineering
- Mixed-Signal-Design-Engineer
- Analog-Design-Engineer
- Principal-ASIC-Design-Engineer
- Principal-Design-Engineer
- Principal-Electrical-Engineer
- Principal-Engineer
Наблюдалась 2026-10-03, впервые 2026-10-03, источник — Himalayas (JSON API).