Post Silicon Performance Architect

We are looking for a hands-on engineer to join our Platform Architecture post-silicon team. This team analyzes and tunes the performance and power of Apple Silicon for the Mac, and takes the learnings and measurements to drive SoC architecture change for future chips. If you work comfortably across the hardware/software stack, and the idea to bring up brand-new chips that just arrived from the fab does not scare you but gets you excited, when we would like to hear from you.

You will join a multidisciplinary team of architecture, silicon design, and system software engineers driving the performance and energy efficiency of Apple SoCs. The work spans application software, system software, SoC architecture, and microarchitecture, and sits at the intersection of measured silicon behavior and forward-looking architecture definition. You will build a deep understanding of how current and planned Apple products behave end to end, and use it to influence both hardware and software direction.

Tune and define SoC memory and fabric performance state controllers on unreleased silicon, and propose improved control and observability mechanisms for future generations. Plan and execute architecture studies that drive performance and energy-efficiency decisions for future SoCs. Build tools, workflows, and automation for repeatable analysis of simulated and measured data, including terabyte-scale traces from prototype devices. Architect hardware features that improve workload characterization and enable robust online control of power and performance. Debug complex interactions between system software and SoC hardware. Assess the feasibility of future use cases, SoCs, and products. Communicate findings across chip design, architecture, software, and system teams to enable data-driven decisions.

BSc, MSc, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field. 3+ years of experience in SoC performance analysis, architecture, or post-silicon characterization. Hands-on post-silicon performance analysis on real hardware, including device capture and trace-based analysis. Working knowledge of SoC memory subsystems, caches, fabric, or power management. Proficiency in C++, Python, and the Unix shell. Ability to work on-site full time at Haifa, Israel. This role requires regular hands-on access to lab hardware and prototype devices and is not eligible for remote work.

Tuning memory performance state controllers, DVFS, or power management policies on pre-production silicon. Depth in one or more of: cache policy, quality of service, clock and power gating, or sleep state control. Debugging system software and SoC interactions across the full stack. Familiarity with processor or SoC design and validation flows, and with industry-standard benchmarks. Use of AI coding tools (e.g., Claude Code) for development and automation. A track record of influencing architecture decisions through data-driven analysis. Effectiveness in ambiguous, fast-paced environments, working both independently and in a small team.