Lead Physical Design Engineer

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Job Description:

Role Overview As a Lead Physical Design Engineer, you will drive physical design implementation for complex SoC architectures on 5nm and advanced sub-5nm technology nodes. This role requires an exceptional balance of hands-on technical execution and strategic engineering leadership. You will own the development and implementation of P&R flows, physical verification, and timing closure, while actively driving methodology improvements and mentoring engineers across different sites and time zones to deliver high-quality silicon.

What You'll Do SoC Integration & Technical Execution Drive top-down/bottom-up physical design integration for complex SoC architectures on 5nm and lower nodes. Adapt quickly to internal P&R methodologies and find opportunities to build industry best practices into existing flows. Execute the full backend flow for block and top, from floorplanning, partitioning, and placement through CTS, routing, and extraction. Own timing and functional ECOs, working collaboratively with signoff teams to push designs toward final closure. Lead and mentor a small physical design team, driving block-level and top-level SoC implementation while keeping the team aligned.

Automation, Leadership & Strategy Build and scale automation flows from scratch as needed, and optimize existing scripts to maximize design re-use. Lead by example, setting clear execution goals, identifying technical bottlenecks early, and establishing engineering benchmarks for the team. Drive tangible improvements in turnaround time, while elevating overall layout and design quality.

What You'll Bring Experience & Core Expertise 15+ years of hands-on experience in physical design and backend digital flows from RTL synthesis down to final GDSII stream-out. High proficiency in timing and physical constraints, ensuring clean translation of design intent into physical layout. Expertise across key design stages at the SoC TOP level, with hands-on proficiency handling EDA tools for floor-planning, partitioning, placement, CTS, routing and full-chip Sign-off Physical Verification (DRC/LVS).

Tools & Automation Mastery Deep technical expertise in advanced backend EDA toolsets, specifically across Cadence, Synopsys, and Siemens (including Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PT, PrimeRail, Voltus, and Redhawk). Strong programming and scripting capabilities, with high proficiency in Tcl and Perl to develop robust, production-grade automation.

Soft Skills & Collaboration Excellent analytical and problem-solving skills to independently debug complex physical and timing closure issues. A proven track record of multi-functional collaboration, with the ability to smoothly align with teams across different geographic sites and time zones.

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