Layout/Mask Designer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Beaverton, Oregon. Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies. Reviewing and analyzing floorplans and complex circuits with circuit designers. Running a complete set of layout design verification tools available on megacells completed. Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Analyzing of LVS, DRC and ERC reports to find the fastest way to complete layouts. Utilizing advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Utilizing advanced layout techniques to come up with best in class PPA for critical designs. Performing EMIR simulations and apply necessary fixes to achieve robust power delivery. Reviewing the layouts designed by peers and provide improvement recommendations. Utilizing automated P&R tools to speed up the layout execution of digital designs. 40 hours/week.

Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electronics Engineering or related field and 2 years of experience in the job offered or related occupation.

2 years of experience with each of the following skills is required:

Utilizing knowledge in layout floor-planning, standard cell planning & hierarchical layout assembly. Applying understanding of issues with RC delay, electro migration, self-heating & cross capacitance to perform optimal wire planning. Recognizing prone layout structures failure and collaborating with other designers to identify solutions. Designing and validating a robust power grid using IR simulation tools to avoid failure prone networks. Interpreting DRC & LVS reports to build manufacturable layout. Utilizing knowledge of cadence virtuoso layout design tools for designing layout structures. Utilizing circuit and layout knowledge in creating low noise, low power data paths and/or memory layout structures.

N/A