CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)
# CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) **Intel** · 2 Locations · `On-site` 🕒 **Статус:** *Опубликовано: сегодня* · *Источник: Intel* --- ### About the Role CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) — 2 Locations
Наблюдалась 2026-09-22, впервые 2026-09-22, источник — Intel.