ASIC III – AMZ010066

MULTIPLE POSITIONS AVAILABLE

Employer: Annapurna Labs (U.S.) Inc. Offered Position: ASIC III – AMZ010066 Job Location: 11815 Alterra Pkwy, Austin, TX 78727 Job Number: AMZ010066

Position Responsibilities: Design and validate high-bandwidth memory and DDR memory physical layer interfaces for machine learning accelerator chips and system-on-chip architectures. Integrate third-party intellectual property blocks into complex system-on-chip designs and perform advanced 2.5D packaging design for memory subsystems. Perform post-silicon validation and characterization of memory subsystems including bring-up, debug, and performance optimization. Define and implement boot-up initialization sequences, reset flows, and training algorithms for memory controllers and physical layer circuits. Collaborate with physical design teams to define timing constraints and review clock distribution networks for memory interfaces. Perform advanced system-level debugging and root-cause analysis of complex functional and performance issues through bring-up, characterization, validation, and production phases. Collaborate with third-party intellectual property vendors and memory device manufacturers to resolve technical issues and optimize performance parameters. Drive cross-functional technical teams to resolve complex functional and performance issues in production environments.

Position Requirements: Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field and seven (7) years of experience in the job offered or related occupation. Employer will accept a Bachelor’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field and nine (9) years of experience in the job offered or related occupation as equivalent to the Master’s degree and seven (7) years of experience. Must have seven (7) years of experience with: silicon development. Must have three (3) years of experience with system-on-chip, input/output subsystems, or memory interface design. Must have experience with: DDR and HBM memory protocols at physical layer and controller level including JEDEC specifications; DDR and HBM training algorithms, timing parameters, and controller configuration features; intellectual property integration and advanced silicon design methodologies; leading cross-functional technical teams to resolve complex functional and performance issues; post-silicon bring-up and validation of input/output and memory interface circuits; and working with third-party intellectual property vendors and memory device manufacturers.

40 hours/week, 8:00am – 5:00pm, Salary Range $202,779 - $215,300 / year.

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